1. Field of the invention
The present invention relates to the testing of memory devices and more particularly to the testing of static random access memory (SRAM) devices, first-in first-out (FIFO) memory devices, and other memories incorporated in integrated circuits.
2. Description of the Prior Art
The premature or infant failure of memory cells in integrated SRAMs, multiple port memories, FIFO memories and other memory products has been an unfortunate but all too common occurrence. Moreover, failure of such parts in the field is unacceptable to vendors of products incorporating integrated circuit memory. As a result, nondestructive testing of all integrated circuits to expose and detect that integrated circuits subject to infant failure is dictated by the market.
One contemporary testing regimen is to place memory devices into burn in oven, elevating the device temperature, and then exercising the devices by applying nominal or stress voltages to the product. For some large capacity memory devices the period in the burn in oven has reached 96 hours, in order to stress each of over one thousand wordlines and millions of memory cells. Such long burn-in cycles pose an obvious bottleneck to production, and are useless for generating up to the minute information about possible faults in the manufacturing process. An accelerated stress mode that eliminates this bottleneck without damaging good memory product would have apparent benefits.
For some test or operating modes of the memory array, selection of all or a portion of row and/or bit lines at a single time is desirable. An example of a test mode where selecting all or a portion of the row and bit lines at a single time is used is described in co-pending U.S. patent application Ser. No. 07/954,276, entitled Stress Test For Memory Arrays In Integrated Circuits, filed Sep. 30, 1992, assigned to SGS THOMSON Microelectronics, Inc. and incorporated herein by this reference. A plurality of rows is selected at one time and a stress voltage is placed on a plurality of bit and complementary bit lines. In this manner the memory cells within the memory array are stress tested in order to detect latent defects.
Another example of test mode, where selecting all the row and bit lines at a single time is used, is described in U.S. Pat. No. 5,341,336 entitled Method For Stress Testing Decoders And Periphery Circuits, assigned to SGS THOMSON Microelectronics, Inc. and incorporated herein by this reference. A plurality of rows and bit lines are selected or deselected simultaneously and a stress voltage is applied to the integrated circuit. In this manner latent defects within decoders and periphery circuits can be detected.
A circuit that allows for the simultaneous selection or deselection of a plurality of rows and columns within a memory array is described in U.S. Pat. No. 5,339,277 entitled Address Buffer, assigned to SGS THOMSON Microelectronics, Inc. and incorporated herein by this reference. A first and a second circuit generate a true and a complementary signal, respectively, during normal operations of the integrated circuit. When desired the first and second circuits may be used to generate two signals of the same voltage level. The two signals of the same voltage level may then be used by an address decoder to simultaneously select or deselect a plurality of rows and/or columns within a memory array.
The increasing complexity of the memory devices is also increasing the number of signal lines that must be controlled during the test and consequently the complexity and the cost of test equipment.
Therefore, it would be desirable to provide a circuit and a method for stress testing integrated memory circuits at wafer level that allows parallel testing of a plurality of integrated circuit dies on a single wafer.
In light of the above, it is an object of the present invention to provide a test circuit that permits parallel testing of a multiplicity of dies on a wafer (e.g. 600 dies/wafer) at the same time and that allows, during the test process, to reveal and discard from the test those dies which go into high current mode. Such a circuit and method would permit at least 600X reduction in test time and also avoid consequent burn in oven insertion of packaged devices, resulting in an important decrease of the test time and of the complexity of test probes and test equipment and verifying reliability of bare silicon dies.